1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, it relates to a technology that may be effectively adopted in a semiconductor integrated circuit device having an SOI (silicon-on-insulator) structure.
2. Description of the Related Art
Today, a technology called SOI is often adopted in semiconductor integrated circuit devices to realize a further reduction in power consumption and faster operation. In the SOI technology in the prior art, an SOI substrate, which is achieved by forming an insulator layer (a buried insulator layer) on a semiconductor substrate and then forming a semiconductor layer via the insulator layer is used. The semiconductor integrated circuit is constituted by forming an impurity area at the semiconductor layer of the SOI substrate and forming a circuit element such as a MOS transistor with the impurity area.
In the SOI technology described above, an SOI substrate having a structure in which the semiconductor substrate and the semiconductor layer at which circuit elements are formed are electrically insulated from one another by the buried insulator layer is used to realize a reduction in power consumption and faster operation.
As a result, there is a problem with semiconductor integrated circuit devices in the prior art in that if a high surge voltage is applied to a circuit element at the semiconductor layer through an external connector terminal or the like, the surge voltage at the semiconductor layer is not transmitted to the semiconductor substrate, resulting in an extremely large difference between the potential at the semiconductor substrate and the potential at the semiconductor layer.
In other words, in a semiconductor integrated circuit device adopting the SOI technology in the prior art, the large potential difference causes a breakdown at the insulator layer present between the semiconductor substrate and the semiconductor layer, and such a breakdown occurring at the insulator layer greatly reduces the reliability of the semiconductor integrated circuit.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device having an SOI structure, with which it is possible to prevent breakdown from occurring at the buried insulator layer and to maintain a high degree of reliability.
In order to achieve the object described above, a first semiconductor integrated circuit device according to the present invention comprises a first circuit element constituted of a semiconductor substrate of a first conductivity type (hereinafter also referred to as xe2x80x9cconduction typexe2x80x9d), a semiconductor layer formed on the semiconductor substrate via an insulator layer, a first element formation area formed at the semiconductor layer, a first impurity area formed at the first element formation area, a second impurity area formed at the first element formation area over a specific distance from the first impurity area and connected to an electrode pad and a first gate electrode provided above the area between the first impurity area and the second impurity area, a first area of a second conduction type formed at the semiconductor substrate under at least either the first impurity area or the second impurity area and a first conductor passing through an insulator layer present between the first or second impurity area and the first area to connect the first or second impurity area to the first area.
A second semiconductor integrated circuit device according to the present invention comprises a first circuit element constituted of a semiconductor substrate of a first conduction type, a semiconductor layer formed on the semiconductor substrate via an insulator layer, a first element formation area formed at the semiconductor layer, a first impurity area formed at the first element formation area, a second impurity area formed at the first element formation area over a specific distance from the first impurity area and connected to an electrode pad and a first gate electrode provided above the area between the first impurity area and the second impurity area, a first area of the first conduction type formed at the semiconductor substrate under the first impurity area and a first conductor passing through an insulator layer present between the first impurity area and the first area to connect the first impurity area to the first area.
A third semiconductor integrated circuit device according to the present invention comprises a first circuit element constituted of a semiconductor substrate of a first conduction type, a semiconductor layer formed on the semiconductor substrate via an insulator layer, a first element formation area formed at the semiconductor layer, a first impurity area formed at the first element formation area, a second impurity area formed at the first element formation area over a specific distance from the first impurity area and connected to an electrode pad and a first gate electrode provided above the area between the first impurity area and the second impurity area, a first area of the first conduction type formed at the semiconductor substrate under the first impurity area, a first conductor passing through an insulator layer present between the first impurity area and the first area to connect the first impurity area to the first area and also passing through the first impurity area and a second conductor formed at a position away from the first conductor over a specific distance, which achieves a potential essentially equal to the potential at the first conductor at the surface of the first impurity area.